My hardware implementation of the DCPU-16 in Verilog RTL

Show HN: My hardware implementation of the DCPU-16 in Verilog RTL

My hardware implementation of the DCPU-16 in Verilog RTL is a business in show hn launch.

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This is a pipelined hardware implementation of the DCPU-16 cpu designed by @notch for his new game 0x10c in Verilog RTL.It is written entirely in RTL Verilog and is fully synthesisable. While basically functional, there is still plenty of room for improvement.Took me a few days of hacking to get it out. I was only focused on functionality so there is plenty of room to reduce chip resource usage - primarily in the EA calculator.I will still continue to work on it in the short term to iron out any kinks.

Within the show hn launch space, the company focuses on its core offering rather than a broad product line.

It is recorded at the Show HN launch stage.

Website: sybreon.github.com/dcpu16