FPGA design acceleration – idiomatic Python to synthesizable Verilog

Show HN: FPGA design acceleration – idiomatic Python to synthesizable Verilog

FPGA design acceleration – idiomatic Python to synthesizable Verilog is active in the show hn launch space.

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Recently I've been working on a certain embedded system that has an FPGA running EKF and some controls. Coding that in RTL is inefficient at best so I turned to HLS and looked around to see what the industry has to offer. I have a pretty extensive simulation and verification scaffold in Python, so ideally I wanted something that can accept Python directly, preferably with minimal adaptation, so that I could feed relevant parts of my Python models to the HLS tool and immediately get a working RTL out. Also I wanted floating point. I should add that my FPGA here is Lattice ECP5 which means that Vitis et al are not an option, so I was focusing on vendor-agnostic tools. There are some that can i

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