Debugging ESP32-S3 watchdog resets caused by flash/cache interactions

Show HN: Debugging ESP32-S3 watchdog resets caused by flash/cache interactions

Debugging ESP32-S3 watchdog resets caused by flash/cache interactions is a company in show hn launch.

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I ran into intermittent interrupt watchdog resets while working on ESP32-S3 firmware(an embedded microcontroller SoC) with flash encryption and PSRAM enabled.What initially looked like a timing or scheduling issue turned out to be a structural problem in ESP-IDF: flash operations temporarily disable cache, while cache sync(`esp_cache_msync`) can still be triggered by DMA-based TLS crypto paths.When these paths overlap, the system can stall long enough to trip the interrupt watchdog.I wrote up the investigation, reproduction conditions, and a workaround(serializing flash operations and cache sync paths) here: https://pazzk.net/blog/esp32s3-flash-cache-issueInterested to hear if others have se

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Website: pazzk.net/en/blog/esp32s3-flash-cache-issue